ISSCC 2006 / SESSION 28 / WIRELINE BUILDING BLOCKS / 28.9 28.9 A 20Gb/s 1:4 DEMUX without Inductors in 0.13μm CMOS
نویسندگان
چکیده
In recent years, high-speed communication systems beyond 10Gb/s have been realized in CMOS technology. A 40Gb/s transmitter including the MUX has been developed in 0.13μm CMOS [1], and a 40Gb/s MUX/DEMUX in 90nm CMOS has been reported [2]. These circuits extend the bandwidth with inductive peaking for 40Gb/s operation. They use supply voltages that exceed the logic supplies used in these technologies. In this paper, a 20Gb/s 1:4 DEMUX in 0.13μm CMOS is presented. This design uses no inductive peaking, which reduces area, and a 1.2V logic supply, which reduces power consumption. A coupled-latch and buffer insertion scheme increases the signal bandwidth at the 20Gb/s data rate. A divide-by-2 circuit uses a DLL to align the clock output of the frequency divider with the data center of the 1:2 DEMUX output. This design reduces the power consumption of the power-hungry divider and improves the timing margin.
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